Non-volatile memories are used in a variety of products because they retain their contents even when power is no longer supplied. An electrically erasable programmable read only memory (EEPROM) is a type of non-volatile memory that permits the contents to be erased and different data to be stored therein.
A typical EEPROM device includes an array of memory cells, and, each memory cell includes a floating gate and a control gate over the floating gate. The floating gate is positioned over a channel of the transistor that is defined between spaced apart source and drain regions formed in a semiconductor substrate. Intervening insulating layers are between the channel and floating gate, and between the floating gate and control gate. One type of memory cell configuration is a stacked gate arrangement wherein the control gate is directly over the floating gate. Another type of memory cell configuration is the split gate arrangement wherein the control gate extends over the floating gate, but also extends laterally adjacent the floating gate over a portion of the channel of the transistor.
A disadvantage of the stacked and split gate arrangements is that they can not be manufactured through the standard complementary metal oxide semiconductor (CMOS) process. This is due to the standard CMOS process using a single layer polysilicon deposition step whereas the stacked and split gate arrangements require two polysilicon deposition steps for the floating gate and the control gate.
A CMOS EEPROM with the control gate and the floating gate formed with a single poly layer is disclosed in U.S. Pat. No. 5,886,376 to Ohsaki and in an article titled "A Single Poly EEPROM Cell Structure For Use In Standard CMOS Process", by Ohsaki et al., IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, March 1994. The disclosed single poly layer memory cell includes adjacently placed NMOS and PMOS transistors. A common polysilicon gate with respect to the NMOS and PMOS transistors serves as the floating gate, and the well region of the PMOS transistor serves as the control gate for the memory cell.
However, there are two problems with erasing a single poly layer memory cell as disclosed in the Ohsaki patent and in the Ohsaki et al. article. One approach to erasing a charge of the floating gate requires a high erase voltage applied to the spaced apart source and drain regions and to the n-well of the PMOS transistor while the NMOS transistor is grounded. When the gate capacitance ratio, i.e., a ratio of the capacitance of the gate of the PMOS transistor to the capacitance of the gate of the NMOS transistor, is much greater than 1, the high erase voltage approaches the junction breakdown voltage of the n-well to the p-well which is about 13 to 15 volts for 0.25 micron technology. A well or tub breakdown reduces device reliability and data retention.
Another approach to erasing a charge of the floating gate requires a high erase voltage applied to the spaced apart source and drain regions of the NMOS transistor while the PMOS transistor is grounded. Depending on the gate capacitance ratio, this high erase voltage approaches the junction breakdown of the PMOS transistor, which is about 7 to 9 volts for 0.25 micron technology. A drain voltage close to the junction breakdown voltage during erase can lead to hole injection into the floating gate, and can thus reduce device reliability and data retention.